1. Filed of the Invention
The present invention relates to a dynamic random access memory device, and more particularly to a dynamic random access memory device having a plurality of input receivers and a micro Ball Grid Array (hereinafter referred to as .mu.BGA) package in which the device is embedded.
2. Description of the Prior Art
A rambus dynamic random access memory (DRAM) commonly includes a plurality of input receivers for transforming input data signals to voltage levels suitable for the operations in the rambus DRAM. Each input receiver generally includes a differential amplifying unit for generating output data signals according to a voltage difference between the corresponding input data signal and a reference voltage. Furthermore, the differential amplifying unit commonly includes a first NMOS transistor having a gate that receives the input data signal and a second NMOS transistor having a gate that receives the reference voltage. The gates of the first NMOS transistors in the input receivers respectively connect (one-to-one) to data input pads of the DRAM. All of the gates of the second NMOS transistors connect to a single reference voltage input pad.
Generally, the gates and drains of the transistors in the input receivers overlap to create parasitic capacitors. As a result, when a plurality of input receivers simultaneously operate, parasitic capacitors formed between the gates and drains of the second NMOS transistors capacitively couple the reference voltage to the output terminals of the differential amplifiers. Changes in the output signals from the differential amplifiers create noise in the reference voltage at the input receivers. If the parasitic capacitance is large, the reference voltage can fluctuate enough to cause false operations of the input receivers. Additionally, the input receivers further from the reference voltage input pad generally suffer from higher noise levels in the reference voltage. As the noise level in the reference voltage gets higher, those input receivers have greater differences in input characteristics and data set-up and hold times.
Accordingly, in the conventional rambus DRAM, an input receiver positioned far from the reference voltage input pad has higher noise levels and requires a greater margin in the data set-up and hold times to avoid false operation.